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Verific Design Automation Adds Renesas Technology

to Customer List

〜HDL Component Software from Verific Implemented in Renesas Internal Development Environment 〜

ALAMEDA, Calif.--(BUSINESS WIRE)--June 2, 2005--Verific Design Automation today announced that Renesas Technology Corp. of Tokyo has selected its hardware description language (HDL) Component Software for use in its internal electronic design automation (EDA) environment.

Verific's ability to support both operations on the parsetree and a fully elaborated netlist from register transfer level (RTL) was an important consideration for Renesas. "This is not an easy requirement," affirms Keiichi Suzuki, senior engineer, System level Design and Verification Technology Dept., LSI Product Technology Unit at Renesas Technology Corp. "Verific's commitment to customer support by the R&D team is commendable. Their dedication ensured that we got the features we needed, and made a significant impact with us."

Renesas develops chips with advanced networking, security, low-power and analog technologies, positioning itself as being at the forefront of ubiquitous networking for mobile technologies, automotive, and PC/audio visual equipment. It purchased source code for Verific's Verilog 2001, VHDL and RTL-to-netlist component software packages, as well as Verific's parsetree software package for its internal development effort. All have been implemented in a state-of-the-art process that makes use of both the netlist and the parsetree.

The Verific software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Its HDL Component Software includes C++ source code-based parsers, analyzers and elaborators for SystemVerilog in addition to Verilog and VHDL.

"We work closely with Renesas due to its advanced use of our parsing software and special customer support requirements," remarks Rob Dekker, president of Verific. "This relationship has given us extraordinary insight into today's design challenges."

Spinnaker Systems Inc., part of the Paltek Group, is Verific's distributor in Japan and negotiated the agreement between Renesas and Verific.

About Verific Design Automation

Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.


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